Fixed incorrect memory clock reported for AMD 19h 60-6fh chipsets.Fixed incorrect memory clock reported for Intel Alder Lake/Rocket Lake chipsets.Fixed channel decoding for AMD Ryzen Zen 2/4 chipsets.Fixed hang due to reading non-existent MSR registers for AMD 19h 60-6fh chipsets.Added support for chipsets with up to 12 memory controllers. ![]()
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